Design and Analysis of 32-bit RISC Processor Based on MIPS
Rama Krishna V1, Venu Gopal B2
1Rama Krishna, ECE Department,JNTUK University, Kaushik College of Engineering, Visakhapatnam, India.
2B.Venu Gopal, Assoc .Professor, Dept. of ECE, Kaushik College of Engineering, visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 05, 2012. | Manuscript published on October 10, 2012. | PP: 17-21 | Volume-1 Issue-5 October 2012. | Retrieval Number: E0279091512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we have studied Microcomputer with out interlocked pipeline stages instruction format instruction data path decoder module function and design theory basend on RISC CPUT instruction set. We have also designed instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module address arithmetic module check validity of instruction module synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on Xilinx Spartan 3Efpga deviceXc3s200.
Keywords: MIPS, Data Flow, Data Path, Pipeline