Open Core Protocol for High Performance on Chip Bus
Asha latha P1, Rambabu B2
1P.Asha latha, ECE Department, JNTUK University, Kaushik College of Engineering, Visakhapatnam, India.
2Ram Babu B, Assoc .Professor, Dept. of ECE, Kaushik College of Engineering, Visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 05, 2012. | Manuscript published on October 10, 2012. | PP: 13-16 | Volume-1 Issue-5 October 2012. | Retrieval Number: E0278091512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The need for on-chip bus protocols are increased drastically for efficient and lossless communication among large number of IP cores of SOC design. This paper proposes a high-performance, highly scalable, bus-independent interface between IP cores named as Open Core Protocol-International partnership. The Open Core Protocol (OCP) is a core centric point to point protocol which provides lossless communication and reduces design time, design risk, and manufacturing costs for SOC designs . Main property of OCP is that it can be configured with respect to the application required. The OCP is chosen because of its advanced supporting features such as configurable sideband control signaling and test harness signals, when compared to other core protocols. The OCP defines a point-to-point interface between two communicating entities such as IP cores and bus interface modules. One entity acts as the master of the OCP instance, and the other as the slave .In this paper, the most efficient bus architecture was adopted to support most advanced bus functionalities including simple transactions, burst transactions, lock transactions, pipelined transactions, and out-of-order transactions withrespect to its suitable application in the real time product. The Open Core Protocol (OCP) was designed and the hardware modeling for that architecture was done using VHDL. This design is Simulated and Synthesized. An experimental result shows the efficiency of the proposed bus architecture and interface.
Keywords: Open core protocolIP Core,SOC,Vhdl