VLSI Implentation of Viterbi Decoder in MIMO Systems
Glory Priscilla1, P.Deepthi2, K.V.Ramana Rao3
1Glory Priscilla, M.Tech ECE Department,JNTU Kakinada University, Pydah College of Engineering and Tehnology, Visakhapatnam, India.
2P.Deepthi, Asst. Professor, Dept. of ECE, Pydah College of Engineering & Technology, India.
3K.V.Ramana Rao, M.Tech ECE Department,JNTU Kakinada University, Pydah College of Engineering and Tehnology, Visakhapatnam, India.
Manuscript received on October 01, 2012. | Revised Manuscript received on October 05, 2012. | Manuscript published on October 10, 2012. | PP: 4-6 | Volume-1 Issue-5 October 2012. | Retrieval Number: E0274091512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems. The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm and increases significantly along with the number of antennas and the modulation order. Consequently, a low-complexity algorithm to mitigate the computational burden is proposed. The design is implemented Xilinx Spartan 3 Xc3s200E fpga and the total power consumed by the device is 0.041W.
Keywords: Branch metrics, MIMO, space-time trellis code, Viterbi decoder.