Implementation of 2D Hartley transform using Distributed Arithmetic
Sai Lakshmi Kumari N1, U.Pradeep Kumar2, K.V.Ramana Rao3
Manuscript received on October 01, 2012. | Revised Manuscript received on October 05, 2012. | Manuscript published on October 10, 2012. | PP: 1-3 | Volume-1 Issue-5 October 2012. | Retrieval Number: E0272091512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Discrete cosine transform (DCT) is usually used in JPEG based image transform coding. This paper presents separable 2-D discrete Hartley transform (SDHT) and its Distributed Arithmetic (DA) based hardware architecture as an alternate to DCT in transform based coding of image compression. The proposed DA architecture for 1-D DHT has very less computations as compared to existing 1-D DCT. The proposed DHT architecture implemented in FPGA indicates a significant hardware savings as compared to FPGA resources used in an efficient memory based DA approach. The additional advantage of SDHT is that its inverse transform is same as forward transform with a constant division. This is demonstrated through a Xilinx FPGA XC3s500E device.
Keywords: Distributed Arithmetic, Discrete Hartley Transform Discrete Cosine Transform, JPEG, Offset Binary Coding.