Design and Implementation of High Speed 16-Bit Approximate Multiplier
M.V.S. Ram Prasad1, B. Suribabu Naick2, Zaamin Zainuddin Aarif3
1M.V.S. Ram Prasad, Department of ECE, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
2Dr. B. Suribabu Naick, Department of ECE, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
3Zaamin Zainuddin Aarif, Department of ECE, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 651-654 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2808028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A multiplier extensively impact on the postpone and strength intake of an arithmetic processor. The accurate results are not usually required in many packages, like records processing and virtual signal processing (DSP). Therefore, the layout of multipliers is in particular centered on speed and power consumption. These parameters are specially finished by way of approximate multipliers. In this paper a new 16 bit approximate multiplier is designed. The partial merchandise of the proposed multiplier are revised and re organized to introduce varying probability phrases. The complexities of the addition of those partial merchandise are reduced based at the possibility. Synthesis results show that the proposed multiplier achieves higher velocity and power consumption in comparison to the preceding precise multiplier.
Keyword: Approximate Computing, Compressors, Multiplier.
Scope of the Article: High Speed Networks