Design and implementation of low power 5 stage Pipelined 32 bits MIPS Processor using 28nm Technology
V.Prasanth1, V.Sailaja2, P.Sunitha3, B.Vasantha Lakshmi4
1V. Prasanth, Pragati Engineering College, Surampalem, Andhra Pradesh, India.
2Dr. V. Sailaja, Pragati Engineering College, Surampalem, Andhra Pradesh, India.
3Mrs. P. Sunitha, Pragati Engineering College, Surampalem, Andhra Pradesh, India.
4Mrs. B. Vasantha Lakshmi, Pragati Engineering College, Surampalem, Andhra Pradesh, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 503-507 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0109028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: MIPS is a simple streamlined highly scalable RISC architecture is most used in android base devices and best suited for portable mobile devices. This Paper presents a design of 5 stage pipelined 32 bit MIPS processor on a 28nm Technology. The processor is designed using Harvard architecture. The most important feature of pipelining is performance and speed of the processor, this results in increase of device power. To reduce dynamic power using RTL clock gating inside FPGA device we presented a novel approach in this paper. Design functionality in terms of area power and speed is analyzed using kintex 7 platform board.
Keywords: RISC,MIPS, Clock Gating, Dynamic Power, FPGA, Pipeling.
Scope of the Article: Evaluation of Glazing Systems for Energy Performance