Multi Attribute Test Pattern Optimization for Test Power Minimization in Digital Circuits
Y.Sreenivasula Goud1, B.K.Madhavi2
1Y.Sreenivasula Goud, Department of Electronics and Communication Engineering, Ravindra College of Engineering for Women, Kurnool, Andhra Pradesh, India.
2Dr. B.K.Madhavi, Department of Electronics and Communication Engineering, Sreedevi Women’s Engineering College, Hyderabad, Telangana, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 233-236 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0050028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Test patterns are the primary bit patterns in need for testing a digital circuitry. Majority of the logical device developed are tested for all functionality before its practical usage. The logical denote and functional complexity has developed new constraint in testing of digital circuit. In developing test patterns for digital test operation, the need of optimal pattern selection are major concern. To develop an optimal test pattern alignment to conserve test power utilization, a new test pattern generation using multi attribute Decision logic and pattern sequencing is proposed. The proposed approach develop a new decision approach in test pattern optimization using the test coverage density and fault test reliability and provide a low power testing approach in digital circuit testing. The simulation result for the proposed system defines the significance of test pattern optimization in power conservation.
Keywords: Test Pattern Optimization, Low Power, Fault test Density, Digital Fault Test Unit (DFTU).
Scope of the Article: Communication