A Multiplication Algorithm
S Subha
S Subha, SITE, Vellore Institute of Technology, Vellore, India.
Manuscript received on January 19, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 3236-3237 | Volume-9 Issue-4, February 2020. | Retrieval Number: D1891029420/2020©BEIESP | DOI: 10.35940/ijitee.D1891.029420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Paper Setup must be in A4 size with Margin: Top 0.7”, Bottom 0.7”, Left 0.65”, 0.65”, Gutter 0”, and Gutter Position Top. Pap Abstract: Multiplication is common arithmetic operation in ALU. Many algorithm are proposed for multiplying two unsigned numbers in literature. This paper proposes algorithm to multiply two unsigned binary numbers of any size. The most significant two bits are used to determine the partial product by bit inspection. The rest of partial products are obtained by suitably shifting the previous partial products and adding the terms involving remainders. The remainder is obtained by taking one bit at a time from the MSB-2 position assuming numbers are indexed from zero in LSB to maximum-1 in MSB. The multiplication process is performed as series of additions, shifts in this method. The proposed method is simulated in Quartus2 Toolkit. It is compared to the in-built multiplication process of the tool. A timing improvement of 9.5% with comparable power consumption is obtained with same pin count.
Keywords: ALU, Multiplication Algorithm, Performance, Power Consumption
Scope of the Article: Algorithm Engineering