Design and Implementation of Ternary Logic Circuits for VLSI Applications
G. Thrishala1, K.Ragini2
1G.Thrishala*, Department of ECE, G. Narayanamma Institute of Technology and Sciences, India.
2K.Ragini, Department of ECE, G. Narayanamma Institute of Technology and Sciences, India.
Manuscript received on January 12, 2020. | Revised Manuscript received on January 21, 2020. | Manuscript published on February 10, 2020. | PP: 3117-3121 | Volume-9 Issue-4, February 2020. | Retrieval Number: C9015019320/2020©BEIESP | DOI: 10.35940/ijitee.C9015.029420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count.
Keywords: Ternary Logic, MVL (Multi-Valued Logic).
Scope of the Article: Digital System and Logic Design