Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC
Chakradhar Adupa1, Chaithanya Mannepalli2, K. Shashidhar3, Srineevasa Rao Ijjada4
1Chakradhar Adupa, Assistant Professor, SR Engineering College, Warangal (Telangana), India.
2Chaithanya Mannepalli, Research Scholar, GITAM Institute of Technology, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
3K. Shashidhar, Research Scholar, GITAM Institute of Technology, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
4Srineevasa Rao Ijjada, Assistant Professor, GITAM Institute of Technology, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 23 November 2019 | Revised Manuscript received on 11 December 2019 | Manuscript Published on 30 December 2019 | PP: 222-225 | Volume-9 Issue-2S3 December 2019 | Retrieval Number: B10561292S319/2019©BEIESP | DOI: 10.35940/ijitee.B1056.1292S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Data plays an important role in the present world where the communications are becoming so crucial. Data acquisition and communication systems are in need ofhigherresolution (i.e., 16 Bits)ADCs. The successive approximation (SAR) ADCis suitable for medium to high range resolution applications, the basic building block of the ADC is Sample and hold circuit which will perform a key role in data conversion from analog data to corresponding digital data.In this paper an operational amplifier with gain 96.5 dB and phase margin of 770 with UGB of 12 MHz is designed to implement high speed and low power sample and hold (S/H) circuit using 0.18 µm SCL CMOS Technology, for higher bit ADC applications with sampling frequency of 10 MHz consuming 182 µW power operating at 3.3 V.
Keywords: ADC, Micro-Power, Sampling Mode, Holding Mode and CMOS.
Scope of the Article: Low-power design