Design & Implementation of E1 to STM-1 Frame and Deframe
Konda Vijayasree1, Siva S Yellampalli2
1Konda Vijayasree, VLSI Design and Embedded Systems, visveswaraiah technological university, UTL Tech. ltd., VTU Extn.center , UTL Technologies, Bangalore, India.
2Dr. Siva S Yellampalli, VLSI Design and Embedded Systems, visveswaraiah technological university, UTL Tech. ltd., VTU Extn.center , UTL Technologies, Bangalore, India.
Manuscript received on July 01, 2012. | Revised Manuscript received on July 05, 2012. | Manuscript published on July 10, 2012. | PP: 188-194 | Volume-1, Issue-2, July 2012. | Retrieval Number: B0182071212/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper describes the design and implementation of E1 frame and generating STM-1 frame multiplexing 64 E1 Frames, as well as degenerating E1 frame from STM-1 frame. The design of Formatter & Analyzer is implemented in Verilog HDL, functionally validated by simulation, carried out by RTL to GDSII tool and synthesized to get resource utilization and implemented on an FPGA for functionality verification, and the power analysis and area calculation of the framer is analyzed using Cadence v6.1.4 and Xilinx 13.2. The designed framer can be used for generation and analysis of E1 frame that has a data rate of 2.048 Mbps and STM-1 frame that has a data rate of 155.52 Mbps.
Keywords: PRBS, E1 frame, scrambler, descrambler, clock divider.