Performance Analysis of Different Topologies of 1-Bit Full Adder in UDSM Technology
J Samanta1, A Patra2, D Mishra3, R Rashmi4, I Kundu5,R Koley6
1Jagannath Samanta, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
2Anurag Patra, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
3Diwakar Mishra, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
4Richa Rashmi, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
5Ishika Kundu, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India
6Ritubrita Koley, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India
Manuscript received on April 20, 2012. | Revised Manuscript received on May 01, 2012. | Manuscript published on July 10, 2012. | PP: 35-41 | Volume-1, Issue-2, July 2012. | Retrieval Number: B0143061212/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adders are key components in digital design, performing not only addition operations, but also many other functions such as subtraction, multiplication and division. Adders of various bit widths are frequently required in Very Large-Scale Integrated circuits (VLSI) from processors to Application Specific Integrated Circuits (ASICs). In this work, we have compared the performance of recently proposed topologies of 1-bit full adders in 150nm technology. We have compared ten different full adder topologies like Standard CMOS, CPL, Leap, LP, Mirror, TGdrivecap, 16Transistor, Conventional, Transmission Gate and 14Transistor full adder. The investigation has been carried out with EDA Tanner SPICE simulation tool. Performance has been also compared for variation of different supply voltage. The analysis has been done on the basis of propagation delay, power consumption and power delay product. The design guidelines have been derived to select the most suitable topology for the design features required.
Keywords: CMOS full adder, Propagation delay, PDP, Topology, UDSM