Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller
Amrut Anilrao Purohit1, Mohammed Riyaz Ahmed2, R. Venkata Siva Reddy3
1Amrut Anilrao Purohit*, Research Scholar, Department of Electronics and Communication Engineering, VTU, Belagavi, India. Assistant Professor, School of Electronics and Communication Engineering, REVA University, Kattigenahalli, Yelahanka, Bengaluru, KTK India.
2Mohammed Riyaz Ahmed, School of Electronics and Communication Engineering, REVA University, Kattigenahalli, Yelahanka, Bengaluru, KTK India.
3R Venkata Siva Reddy, School of Electronics and Communication Engineering, REVA University, Kattigenahalli, Yelahanka, Bengaluru, KTK India.
Manuscript received on October 12, 2019. | Revised Manuscript received on 22 October, 2019. | Manuscript published on November 10, 2019. | PP: 4763-4768 | Volume-9 Issue-1, November 2019. | Retrieval Number: A4588119119/2019©BEIESP | DOI: 10.35940/ijitee.A4588.119119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half.
Keywords: Area Optimization, Communication Protocol, Serial Peripheral Interface, Structural Modeling
Scope of the Article: Communication