Pipelining Based Floating Point Division: Architecture and Modeling
Santanu Halder1, Abul Hasnat2, Azizul Hoque3, Debotosh Bhattacharjee4, Mita Nasipuri5
1Dr. Santanu Halder, Assistant Professor, Department of Computer Science and Engineering, Government College of Engineering Textile Technology, Berhampore (West Bengal), India.
2Mr. Abul Hasnat, Assistant Professor, Department of Computer Science and Engineering, Government College of Engineering Textile Technology, Berhampore (West Bengal), India.
3Azizul Hoque, Research Scholar, Kalyani University, (West Bengal), India.
4Dr. Debotosh Bhattacharjee, Associate Professor, Department of Computer Science and Engineering, Jadavpur University, Kolkata (West Bengal), India.
5Dr. M. Nasipuri, Professor, Department of Computer Science and Engineering, Jadavpur University, Kolkata (West Bengal), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 15-19 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0870063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, an efficient FPGA based architecture for a fractional division based on Newton-Raphson method for IEEE single-precision floating point number is presented. With advent of more graphic, scientific and medical applications, floating point dividers have become indispensable and increasingly important. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this work, highly optimized pipelined architecture of an IEEE-754 single precision floating point divider is designed to achieve high frequency on FPGA. The division is performed by multiplying the numerator by the reciprocal value of the denominator and the initial approximation of the denominator is obtained from a Look-up Table.
Keywords: FPGA, Newton-Raphson Method, IEEE 754 Single Precision Format, VHDL.
Scope of the Article: Next Generation Internet & Web Architectures