Modified Multicast Routing Algorithm for Network-on-Chip
K.Shoukath Ali1, P.Samapth2, S.Elango3, Sajan P Philip4
1K.Shoukath Ali, Bannari Amman Institute of Technology, Sathyamangalam, (TamilNadu), India.
2P.Samapth, Bannari Amman Institute of Technology, Sathyamangalam, (TamilNadu), India.
3S.Elango, Bannari Amman Institute of Technology, Sathyamangalam, (TamilNadu), India.
4Sajan P Philip, Bannari Amman Institute of Technology, Sathyamangalam, (TamilNadu), India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 208-210 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0043028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, the Multicast Routing (MR) algorithm problem for Networks-on-Chip (NOC) is studied and an efficient routing algorithm is proposed. Here each and every MR step is designed as a Minimum Directed Spanning Tree (MDST) Problem. The MDST capably finds the best routing solutions for multicast flows. Power consumption is one of the major evaluation parameter for routing inside Network-on-Chip (NOC). The power consumption mentioned here includes both leakage power and dynamic switching power. Simulation is performed over several randomized network layouts and the results are compared with conventional PIM-DM. In particular, the proposed algorithm achieves a 24% reduction in power consumption over conventional PIM-DM when the number of computational cores inside a chip is nearly hundred.
Keywords: Minimum Spanning Tree, Shortest Arborescence, Leakage Power, Dynamic Switching Power, Computational Cores.
Scope of the Article: Computational Techniques in Civil Engineering