FPGA Implementation of GPS Location Based Secured Data Accessing System
Fazal Noorbasha1, M. Sai Devansh2, M. Vinay Kumar3, A. Surya Kiran4, G. Sree Pavani5, K Hari Kishore6
1Fazal Noorbasha, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
2M. Sai Devansh, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
3M. Vinay Kumar, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
4A. Surya Kiran, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
5G. Sree Pavani, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
6K Hari Kishore, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 124-127 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60360486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Now a day’s Field Programmable Gated Array (FPGA) are advanced architectures for various cryptographic systems and algorithm applications. Due to the reprogrammable flexibility of FPGAs, the advanced cryptographic algorithms are exploited to achieve high throughputs at the expense of very low chip area. The security can be improved by using standardized and proven-secure block ciphers like advanced encryption standard (AES). In this paper, we had designed our hardware optimization strategies for AES for high-speed, low-power algorithm for IoT applications with multiple levels of security. Main objective of action includes having user location data in the form of latitude/longitude followed by incorporating that with a randomly generated key for encryption. Receiver can only access the data of the host system and decrypt the cipher text only if the location coordinates and keys are matched.
Keywords: AES, GPS Location, Data, FPGA, Verilog HDL.
Scope of the Article: Communication