Static Timing Analysis and Timing Violations of Sequential Circuits
G.Siva Priya1, K.Hari Kishore2, Fazal Noorbasha3
1G. Siva Priya, Department of Computer Science and Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
2K. Hari Kishore, Department of Computer Science and Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
3Fazal Noorbasha, Department of Computer Science and Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
Manuscript received on 04 May 2019 | Revised Manuscript received on 09 May 2019 | Manuscript Published on 13 May 2019 | PP: 115-121 | Volume-8 Issue-7S May 2019 | Retrieval Number: G10240587S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Designing of sequential circuits needs timing analysis at each and every stage of design process (synthesis, floor planning, placement, routing, layout design and comprises of three main parts-Timing checks, Constraints and Libraries. Timing checks such as setup (Ts) and hold time (Th) violation check in sequential circuits plays an important role during timing verification. This paper describes about static timing analysis mainly about reg2reg setup and holds analysis and analyses a kind of detection and correction circuits for Ts and Th violations [1] by associating a digital circuit to them.
Keywords: Timing Parameters, Static Timing Analysis, Additional Pessimism, on-Chip Variations.
Scope of the Article: Computer Science and Its Applications