Survey on Routing Algorithms for Fault Tolerant in Network on Chip
Devendra Rapelli1, J. L .Mazher Iqbal2
1Devendra Rapelli, Research scholar, Department of Electronics and Communications Engineering, Vel Tech, Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai (TamilNadu), India.
2Dr. J. L .Mazher Iqbal, Professor, Department of Electronics and Communications Engineering, Vel Tech, Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai (TamilNadu), India.
Manuscript received on 15 May 2019 | Revised Manuscript received on 22 May 2019 | Manuscript Published on 10 July 2019 | PP: 429-433 | Volume-8 Issue-7C2 May 2019 | Retrieval Number: G10930587C219/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Latest styles in VLSI study areas archives a variety of cores systems are built-into solitary chip silicon processor in circumstances of submicron gadget. Also these multi main systems are undertaking huge parallel computation process efficiently using Network on Chip architecture. As a router its fundamental duty is to get rid of the whole delay and in addition power dissipation. In this research paper we will explain usuall router strategies and various issues with their operating strategies and propose new ideas for enhancing its efficiency.
Keywords: Network On Chip; Round Robin Arbitration; Dynamic Router; Processing Element.
Scope of the Article: Communications