Host Based System C-TLM2.0 Simulation Model for Memory Device Driver Verification
A. Pallavi1, C. Kanagasabapathi2, Siva S Yellampalli3
1A. Pallavi, VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
2C. Kanagasabhapati, VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
3Dr. Siva S Yellampalli, VLSI design and Embedded Systems, UTL Technologies Ltd, Bangalore, Karnataka, India.
Manuscript received on 02 July 2019 | Revised Manuscript received on 16 July 2019 | Manuscript Published on 23 August 2019 | PP: 260-263 | Volume-8 Issue-9S3 August 2019 | Retrieval Number: I30470789S319/2019©BEIESP | DOI: 10.35940/ijitee.I3047.0789S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With increasing complexity in SoC architecture in today’s embedded systems demand for more software applications is increasing. Time to market plays an important role for any product to win the market. Device drivers and stability pre-silicon (prior to silicon arrival) plays a very important role. To develop, integrate, system test and debug device drivers like Memory, I2C, PCIE, USB etc. with real world use cases, availability of hardware board is necessity. Availability of hardware board traditionally happens towards the later stages of the project life cycle. The best solution is using SystemC-TLM2.0 simulation models to verify device drivers early. This ensures the readiness of device drivers even before the hardware availability and effectively reduces time to market (TTM). Aim of this thesis is to develop Host based SystemC-TLM2.0 simulation model for Memory device driver verification.
Keywords: System C, TLM2.0, TTM, Memory device drivers
Scope of the Article: Digital Clone or Simulation