Accounting for PVT Variations in Design Timing Closure
Vasanth Mundargi1, Siva Yellampalli2
1Vasanth Mundargi, Post Graduate Student, UTL Technologies Ltd, VTU Extension Center, Bengaluru, India.
2Dr. Siva Yellampalli, Principal, UTL Technologies Ltd, VTU Extension Center, Bengaluru, India.
Manuscript received on 02 July 2019 | Revised Manuscript received on 16 July 2019 | Manuscript Published on 23 August 2019 | PP: 236-240 | Volume-8 Issue-9S3 August 2019 | Retrieval Number: I30420789S319/2019©BEIESP | DOI: 10.35940/ijitee.I3042.0789S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The On Chip Variation (OCV) refers to changes in the behavior of parameters like process, voltage and temperatures on a chip. In this paper, we go through different approaches followed to compensate for PVT variations on chip during design timing closure. We review the dominant approaches used for accounting such variations. We also review the advantages and disadvantages of these approaches used based on the ease of use, implementation, power, area, and the overheads involved in adopting them.
Keywords: Delays, PVT variation, Static Timing Analysis, On-Chip Variation, Derating, AOCV, LOCV, GBA, PBA, IR Drop, Voltage Aware STA
Scope of the Article: Predictive Analysis