Implementation of Low Power and Area Efficient Vedic Multiplier
Shobana Priya M S1, Manikandan T2, Joshua Kumaresan S3, Satheesh Kumar S4, Muruganandham A5
1Ms. M. S. Shobana Priya, M.E., Ph.D, Assistant Professor, Department of ECE, Saveetha School of Engineering, India.
2Dr. T.Manikandan, Professor, Department of ECE, Rajalakshmi Engineering College, Mevalurkuppam (Tamil Nadu), India.
3Dr. S. Joshua Kumaresan, Associate Professor, Department of ECE, R.M.K. Engineering College, (Tamil Nadu), India.
4Mr. S. Satheesh Kumar, Assistant Professor, Department of ECE, Sri Krishna College of Engineering and Technology, Coimbatore (Tamil Nadu), India.
5Dr. A. Muruganandham, Professor, Department of ECE, Rajarajeswari College of Engineering, Bengaluru, (Karnataka), India.
Manuscript received on 23 November 2019 | Revised Manuscript received on 04 December 2019 | Manuscript Published on 14 December 2019 | PP: 206-209 | Volume-9 Issue-1S November 2019 | Retrieval Number: A10421191S19/2019©BEIESP | DOI: 10.35940/ijitee.A1042.1191S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.
Keywords: Multiplier, CMOS, Full Adder, Low Power, Small Area.
Scope of the Article: Low-power design