Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate NanoFET
Kuleen Kumar1, Rudra Sankar Dhar2
1Kuleen Kumar, Pursuing Ph.D, Department of Electronics and Communication Engineering, National Institute of Technology, (Mizoram), India.
2R. S. Dhar, Assistant Professor, Department of ECE, NIT (Mizoram), India.
Manuscript received on 03 December 2019 | Revised Manuscript received on 11 December 2019 | Manuscript Published on 31 December 2019 | PP: 113-116 | Volume-9 Issue-2S December 2019 | Retrieval Number: B10701292S19/2019©BEIESP | DOI: 10.35940/ijitee.B1070.1292S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.
Keywords: HOI MOSFET, Lattice Mismatch, Strained Silicon, Work Function.
Scope of the Article: Network Modelling and Simulation