Reconfigurable Down Sampling Channelizer for SDR Receiver Using FPGA
Majid S. Naghmash1, Hazim Salah Abdulsatar2, Tahseen Flaih Hasan3
1Dr. Majid S. Naghmash, Department of Power Electrical and Electronic Engineering, College Foundation of Technical Education, Baghdad Iraq.
2Hazim Salah Abdulsatar, Department of Electronic Techniques, Institute of Technology, Foundation of Technical Education, Baghdad Iraq.
3Tahseen Flaih Hasan, Department of Electronic Techniques, Institute of Technology, Foundation of Technical Education, Baghdad Iraq.
Manuscript received on 11 January 2014 | Revised Manuscript received on 20 January 2014 | Manuscript Published on 30 January 2014 | PP: 23-27 | Volume-3 Issue-8, January 2014 | Retrieval Number: H1430013814/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents, the design and implementation of reconfigurable down sampling the IF band frequency to baseband in Software Defined Radio (SDR) receiver. To enhance both the integration and adaptation of multiple communication standards like GSM, CDMA and WCDM systems, the selection of channel in SDR technology require to achieve relaxing on chip at baseband. The wireless and mobile systems classically utilize a channelizer to extract the desired band for more processing in baseband. Down conversion in frequency domain requires less computation and complexity to provide the idea of minimum power consumption as current user demand. In the low power design and efficient FPGA area implementation, the cascaded digital filter structure is required to convene multi standards specifications in wide and narrow band systems. Many type of digital filter has been decomposition to implement this filter as well as a lot of software from Mathworks and Xilinx is used. A number of experiments and investigation are given to estimate the results of FPGA design for filter structure. The nonappearance of error in the design steps shows an important improvements in the filter implementation results to enhance the conventional design.
Keywords: Reconfigurable Filter, Down Sampling, SDR Receiver, FPGA.
Scope of the Article: Reconfigurable Computing