Multi-Level Memristor Memory: Design and Performance Analysis
Pooja G1, S. Murali Krishna2, V. Ravi3
1Pooja G, Department of Electronics Engineering, Vellore Institute Technology, Chennai (Tamil Nadu), India.
2S.Murali Krishna, Department of Electronics Engineering, Vellore Institute Technology, Chennai (Tamil Nadu), India.
3V.Ravi, Department of Electronics Engineering, Vellore Institute Technology, Chennai (Tamil Nadu), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 723-729 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2826028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memristor-based memories are one of the attractive candidates to replace present memory technologies due to its novel characteristics such as non-volatile storage, nanosize cell, compatibility with CMOS, low power dissipation, and multi-level cell (MLC) operation etc. However, the device needs to overcome the potential challenges such as process variations, non-deterministic nature of the operation, sneak path issues, non-destructive write and read operation. One of the most important characteristics of memristor memories is its ability to store multiple bits in one cell. In this paper, we design a low power, high-speed multi-level memristor based memories. Additionally, the performance analysis of the multi-level memristor memories has been performed under various memristor models and window functions.
Keyword: Memristor, Non-volatile Memory.
Scope of the Article: Measurement & Performance Analysis