PV Variations of Pulsed Latch Circuits
M.Aditya1, P. Bhavitha2, P. Gopi3, P. Kiran Babu4, P. Pavan5, B. Teja Sai Varma6
1M. ADITYA, Assistant Professor, KLEF, KL Deemed to Be University, Guntur (Andhra Pradesh), India.
2P. BHAVITHA, Undergraduate Student, Recent works PV Variations of Pulsed Latches.
3P. GOPI, Undergraduate Student, Recent works PV Variations of Pulsed Latches.
4P. KIRAN BABU, Undergraduate Student, Recent works PV Variations of Pulsed Latches.
5P. PAVAN, Undergraduate student, Recent works PV Variations of Pulsed latches
6B.Teja Sai Varma, Undergraduate Student, Recent works PV Variations of Pulsed latches.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 859-862| Volume-8 Issue-6, April 2019 | Retrieval Number: E3239038519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper we studied the change in the result or action of different PV variations on the behaviour of Pulsed Latches by taking the reaction on both the Pulser and the Latch. Pulsed Latches are gaining reduced delay and power consumption in low power ASIC design technology. They provide another sequential element with high performance and low area and power consumption, taking advantage of both latchs and flip-flop features. This process implements the pulser by using MUX based pulser design. This design approaches are presented to improve the quality of Pulsed Latches circuits by using their main importance of high performance, low power, and small area. The proposed design has low power variation when operating at normal supply voltage.
Keyword: Pulsed Latches, Variability, Process Variation, Scaling of Voltage, Less Power.
Scope of the Article: Bio-Science and Bio-Technology