A Detailed Scrutiny and Reasoning on VLSI Binary Adder Circuits and Architectures
K Mariya Priyadarshini1, R. S. Ernest Ravindran2, P. Ratna Bhaskar3
1K Mariya Priyadarshini, PhD in Koneru Lakshmaiah Educational Foundation, Deemed to be University, Andhra Pradesh, India.
2Dr. R.S. Ernest Ravindran PhD in 2016 from Anna University, Chennai, India.
3P. Ratna Bhaskar, PhD in Koneru Lakshmaiah Educational Foundation, Deemed to be University, Andhra Pradesh, India.
Manuscript received on 05 May 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 887-895 | Volume-8 Issue-7, May 2019 | Retrieval Number: F3379048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this document a survey on recent developments in the design of binary adders is done. Adders are the core cells of any arithmetic unit which define the speed of any processor. The motivation of this paper is to focus on different kinds of architectures of higher order binary adders that provide high speed, less power to increase the level of integration on any integrated circuits (IC). Though there are many algorithms proposed for improving the speed of an adder the challenges still remain in designing fast and accurate adders. At the schematic level we scrutiny six different adders for high speed and low power applications.
Keyword: Carry Propagation delay, Fast Adder Principles, Carry Selection, Carry Skip, Prefix adders.
Scope of the Article: VLSI Algorithms