Implementation of Most Appropriate Leakage Power Techniques in Vlsi Circuits Using Nand and Nor Gates
M.Siva Kumar1, Syed Inthiyaz2, P.Venkata Krishna3, Ch. Jyothsna Ravali4, J. Veenamadhuri5, Y.Hanuman Reddy6, Sk. Hasane Ahammad7
1M.Siva Kumar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
2Syed Inthiyaz, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
3P.Venkata Krishna, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
4Ch. Jyothsna Ravali, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
5J.Veenamadhuri, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
6Y.Hanuman Reddy, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
7Sk. Hasane Ahammad, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P.), India.
Manuscript received on 05 May 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 797-801 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5905058719/19©BEIESP
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Abstract: The speedy boom of semiconductor generation and growing call for portable devices powered gadgets via battery has led the constructors to scale back the capabilities size resultant decreased threshold voltage in addition to there by way of enabling integration of relatively complex capability on a single chip. In each technological and implementation components Chip’s most strength method is adopted. Sleepy stacked with LECTOR technique. This includes leakage control transistor introduced between pull up and pull down circuit.The Stack effect might be brought through substituting every current transistor with two half of sized transistor. It supplies the challenge of the location because of utilization of greater transistor toward keeping the circuit kingdom at some point of sleep mode. As CMOS era scales down, the supply voltage must be decreased such that dynamic energy may be kept at realistic degrees.
Keyword: LECTOR technique, CMOS.
Scope of the Article: VLSI Algorithms