Asic Implementation of High Speed Discrete Integrator Using Vedic Mathematics
R. Anitha.1, V. Bagyaveereswaran2
1R. Anitha, Department of Electronic and Communication Engineering from Periyar University, Salem, (Tamil Nadu), India.
2V. Bagyaveereswaran, Department of Instrumentation and Control Engineering from Madurai Kamaraj university, Madurai, (Tamil Nadu) India.
Manuscript received on 01 June 2019 | Revised Manuscript received on 07 June 2019 | Manuscript published on 30 June 2019 | PP: 2246-2252 | Volume-8 Issue-8, June 2019 | Retrieval Number: H7150068819/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Vedic Mathematics is an ancient Indian mathematics which has unique technique for arithmetic computation. An ASIC based discrete integrator is designed in this paper. This is a novel architecture employs less numbers of multipliers when compared with the conventional one. The architecture could be used in 16-bit ALU. This research used cadence ncsim, rc compiler tool and 90nm technology for synthesis. This paper reveals the study of Vedic multiplier for 16, 32 & 64 bits which is totally unconventional method than shift add. A single architecture also can be used for squaring, cubing as well as Reimann Integral Theorem up to order 4.
Keywords: Discrete Integrator, Vedic Mathematics, ALU, High Speed, Accuracy, Reusabilty
Scope of the Article: Applied Mathematics and Mechanics