Energy Efficient SRAM
Niharika Karana1, Shreela Dubey2, Shobha Sharma3, Amita Dev4
1Niharika Karana, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, Delhi, India.
2Shreela Dubey, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, Delhi, India.
3Dr. Shobha Sharma, Corresponding Author, Faculty, Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, Delhi, India.
4Prof Amita Dev, Pro VC, IGDTUW, Delhi.
Manuscript received on 31 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1086-1091 | Volume-8 Issue-9, July 2019 | Retrieval Number: I7756078919/19©BEIESP | DOI: 10.35940/ijitee.I7756.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.
Index Terms: Static Random Access Memory, Static Noise Margin, Adaptive Voltage Level Technique, Multi-Threshold CMOS.
Scope of the Article: Renewable Energy Technology