Implementation of Low density Parity Check system using Probabilistic Gradient Descent Bit Flipping Decoder
Venkateswara Rao Varri1, N. Arun Vignesh2, Asisa Kumar Panigrahy3, C H Usha Kumari4
1Venkateswara Rao Varri, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad
2N. Arun Vignesh, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad
3Asisa Kumar Panigrahy, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad
4C H Usha Kumari, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad
Manuscript received on 02 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 2005-2009 | Volume-8 Issue-10, August 2019 | Retrieval Number: J93090881019/2019©BEIESP | DOI: 10.35940/ijitee.J9309.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper represents the concept of hard decision decoder in which PGDBF is suitable decoder for the basic model of hard-choice decoder as long as low-density parity check code (LDPC) which is increase the error correction. This design introduced dynamic architecture which reduce the capability of random disarrangement of the PGDBF. The design is working on the Short Random Sequence (SRS) that is replica cover on the PGDBF decoding guidelines. In each iteration flipping number of bits these are focusing on improvement in performance and decoding delay. The best SRS is essential to manage the wellknown decoding achievement of PGDBF, we introduced two kind of access with same hardware categories, but various LDPC codes are perform different behaviors. In this design we are modifying small hardware decoding unit for obtaining a good decoding explanation for present and further purpose.
Keywords: Gradient-Descent bit flipping, low-density parity-checker, Irregular generator.
Scope of the Article: Low-power design