Design of Efficient Complex Gate using 45nm Technology
Sudhakar Alluri1, D.Mamatha, K.Mounika2
1Sudhakar Alluri is with the electronics and communication engineering Department, CMR Institute of Technology, Hyderabad, T.S, India.
2D.Mamatha, is with the ECE, CMR Institute of Technology, Hyderabad, TS, India.
3K.Mounika, is with the ECE, CMR Institute of Technology, Hyderabad, TS, India.
Manuscript received on November 18, 2019. | Revised Manuscript received on 27 November, 2019. | Manuscript published on December 10, 2019. | PP: 3583-3588 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7569129219/2019©BEIESP | DOI: 10.35940/ijitee.B7569.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we designed complex gate which is having very good performance in terms of delay. This is achieved by increasing threshold voltage. The reduced delay and its percentage variation with respect to threshold voltage is shown below in the result analysis. Increasing of threshold voltage not only reduces delay but indirectly reduces leakage power consumption. Now-a-days Efficient Complex Gate using 45nm technology is preferable because of its delay and power.
Keywords: Complex gate, Low Power, Delay , DSP, VLSI.
Scope of the Article: Low-power design