Design of Multiplier through Modified Booth Algorithm with Mig Gate
Ripunjai Gurava1, P. Suresh Babu2
1Ripunjai Gurava, M. Tech (VLSI System Design), VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad.
2P. Suresh babu, Ph. D, Acharya Nagarjuna University, Guntur.
Manuscript received on November 16, 2019. | Revised Manuscript received on 24 November, 2019. | Manuscript published on December 10, 2019. | PP: 3101-3105 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7476129219/2019©BEIESP | DOI: 10.35940/ijitee.B7476.129219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper compares different Booth multipliers i.e., Radix-2, 4, 8 is designed using a new carry look-Ahead adder (CLA). In this Delay and Power have been compared and the main aim behind the project is developing Booth multiplier using Reversible Logic Gate (RLG).While comparing with the normal multiplication, Modified Booth Algorithm gives the less amount of delay as the number of partial products gets reduced. In this process CLA is used to reduce the overall multiplier Delay.The reversible logic is considered because it reduces the circuit complexity, loss of information and power consumption. In this paper a new CLA architecture is proposed in place of the existing CLA architecture which exhibits a high performance of computation, power consumption and area. In this architecture, Delay and power consumption of the design are reported. This new architecture is simulated and synthesized using Xilinx ISE environment.
Keywords: Booth multiplier, Carry Look-Ahead adder (CLA), Reversible Logic Gates (RLG).
Scope of the Article: Algorithm Engineering