Full Adders using GDI (With Full Swing) Technique for Power Efficient Computing
M Lakshmana Kumar1, M Aditya2, Degala Kavya Vineela3, Battini Ramesh Reddy4, B Vijaya Lakshmi5, K.S.S.S.L Bhargavi6
1M. Lakshmana Kumar, Assistant Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
2M.Aditya, Assistant Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
3Degala Kavya Vineela, Student, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
4Battini Ramesh Reddy, Student, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
5B.Vijaya Lakshmi, Student, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
K. S. S. S. L Bhargavi, Student, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
Manuscript received on November 16, 2019. | Revised Manuscript received on 20 November, 2019. | Manuscript published on December 10, 2019. | PP: 3011-3016 | Volume-9 Issue-2, December 2019. | Retrieval Number: B6651129219/2019©BEIESP | DOI: 10.35940/ijitee.B6651.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adders, Multiplexers and other arithmetic circuits have a crucial role in Digital Signal Processing and various real time applications. Among those, Full adder is a central for most of the digital operations that perform subtraction or addition. Major component is Adder with High performance and a power efficient in specific applications. In this paper, the adder with high performance and power efficient are designed using Gate Diffusion Logic which reduces threshold voltage problem. We designed the circuits with minimum power consumption and with high performance efficiency. For the simulation of the circuits Mentor Graphics with 130nm technology is used. The obtained result shows that the proposed designs consume the minimum power when compared to other designs which are taken for the comparison.
Keywords: Hybrid full Adder, GDI full Adder, Full Swing GDI, Energy Efficient Adder.
Scope of the Article: Cloud Computing