Design of XOR and XNOR Based Full Adder Circuits
Inumula Veerarahava Rao1, Aditya M2, V Kavya Chowdary3, K Sai Nishitha4, V Naveen Sai5
1I.Veeraraghava Rao, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India
2Aditya M, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India
3V Kavya Chowdary, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India
4K Sai Nishitha, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India
5V Naveen Sai, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
Manuscript received on November 15, 2019. | Revised Manuscript received on 20 November, 2019. | Manuscript published on December 10, 2019. | PP: 2434-2437 | Volume-9 Issue-2, December 2019. | Retrieval Number: B7003129219/2019©BEIESP | DOI: 10.35940/ijitee.B7003.129219
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Abstract: This paper has a XOR / XNOR gate circuits produces separate and establishes a simultaneous XOR – XNOR function.. Due to stubby yield capacity and short-circuit energy dissipation, the power utilization and latency of these circuits is increasing A new one-bit adder hybrid circuit is chosen built on the effective gates of xor xnor or xor / xnor. Each prefer circuit has its own advantages as it is known for its high speed, low current drain, short delay product (PDP), galvanic ability, etc. Simulations of the planned models were carried out using Mentor Graphics to see the quality of these projects. The simulation results are based on the 130-nm CMOS engineering design. A recent technique of transistor sizing is implemented to improve the circuits ‘ PDP.
Keywords: Transistor Sizing Method, PSO, XOR–XNOR, Output Driving Capability, DPL
Scope of the Article: Nanometer-Scale Integrated Circuits