Effective CU Design Based Implementation of a 64-Bit Processor for Signal Processing Applications
P. Anandan1, C. H. Mohan Sai Kumar2, B. Venkataramanaiah3
1Dr. P. Anandan*, Assistant Professor, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai, Tamil Nadu, India
2C. H. Mohan Sai Kumar, Assistant Professor, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, chennai, Tamil Nadu, India.
3B. Venkataramanaiah, Assistant Professor, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai, Tamil Nadu, India.
Manuscript received on December 15, 2019. | Revised Manuscript received on December 20, 2019. | Manuscript published on January 10, 2020. | PP: 2344-2347 | Volume-9 Issue-3, January 2020. | Retrieval Number: A4175119119/2020©BEIESP | DOI: 10.35940/ijitee.A4175.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The aim of this paper is to design simple and Effective digital control unit for a 64-bit processor core. Proposed idea is implemented in Spartan-III FPGA Architecture. Control unit (CU) directs the operation of the processor to get results. The function of CU is to fetch their instructions, examining them and execute the programs stored in the memory and executing them one after another in Main Memory. The Central Processing Unit (CPU) is the combination of Arithmetic and Logic Unit (ALU) and CU. The CPU receives information from several different elements; they are memory, control path and data path. Control Unit is required to produce the control signals for operating data path at each clock cycle. CU generates instructions to the memory, arithmetic/logic unit and input and output devices. The proposed control unit simulated in Xilinx and implemented in Spartan 3E , achieved less delay compared to existing approaches
Keywords: CPU, ALU, FPGA, RISC, REGISTER, CONTROL BUS.,CU
Scope of the Article: Digital Signal Processing Theory