Loading

Design a Full Adder Circuit using Modernized Full Sway Exclusive-Or and Exclusive-Nor Gates in 130nm Mentor Graphics
Venkata Yashwanth Goduguluri1, Guntupalli Sai Divya Madhuri2, Balusupati Bhanu Pranavi3, Bhimineni Kalyani4, Annam Sai Anusha5

1Venkata Yashwanth Goduguluri*, Assistant Professor, KKR&KSR Institute of Technology and Sciences, Vinjanampadu, Guntur, India.
2Guntupalli Sai Divya Madhuri, KKR&KSR Institute of Technology and Sciences, Vinjanampadu, Guntur, India.
3Balusupati Bhanu Pranavi, KKR&KSR Institute of Technology and Sciences, Vinjanampadu, Guntur, India.
4Bhimineni Kalyani, KKR&KSR Institute of Technology and Sciences, Vinjanampadu, Guntur, India.
5Annam Sai Anusha, KKR&KSR Institute of Technology and Sciences, Vinjanampadu, Guntur, India.
Manuscript received on December 15, 2019. | Revised Manuscript received on December 20, 2019. | Manuscript published on January 10, 2020. | PP: 2327-2332 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8844019320/2020©BEIESP | DOI: 10.35940/ijitee.C8844.019320
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this manuscript, new circuits for XOR/XNOR and concurrent XOR-XNOR purposes are designed. The designed trails are elevated lessened in expressions of the power usage and delay, which are appropriate to low harvest capacitance and low short-circuit power wastage. The designed new hybrid 1-bit full-adder (FA) trails related on the new full sway XOR-XNOR gates. Every designed circuit give their prospective advantages in period of speed, power usage, power delay product (PDP), and dynamic facility and so on. To know the performance of the intended designs, wide-ranging Mentor graphics simulations are carried out. The replications outcomes, supported on the 130-nm CMOS knowledge signify the intended intends have higher rapidity and power over supplementary FA devises. An innovative transistor sizing mode is accessed to reduce the PDP of the tracks. In the designed process, the algebraic working out particle swarm optimization module is utilized to obtain the preferred assessment for finest PDP with less iteration. The designed tracks are checked in times of dissimilarities of the supply, threshold voltages, input noise immunity and size of transistors. 
Keywords: Full Adder (FA), Noise, Transistor Sizing Method, EXOR-EXNOR.
Scope of the Article: Computer Graphics, Simulation, and Modelling