VLSI Architecture of High Performance Multiplier for High Speed Applications
J.M.Mathana1, R.Menaka2, R.Dhanagopal3, B.Sundrambal4
1Dr.J.M.Mathana, Professor, Dept. of Electronics and Communication Engineering, Chennai Institute of Technology, Kundrathur, Chennai, Tamil Nadu, India.
2Dr.R.Menaka, Professor, Dept. of Electronics and Communication Engineering, Chennai Institute of Technology, Kundrathur, Chennai, Tamil Nadu, India.
3Dr.R.Dhanagopal, Associate Professor, Dept. of Electronics and Communication Engineering, Chennai Institute of Technology, Kundrathur, Chennai, Tamil Nadu, India
3Dr.B.Sundrambal, Professor, Dept. of Computer Science and Engineering, Chennai Institute of Technology, Kundrathur, Chennai, Tamil Nadu , India
Manuscript received on December 17, 2019. | Revised Manuscript received on December 27, 2019. | Manuscript published on January 10, 2020. | PP: 442-445 | Volume-9 Issue-3, January 2020. | Retrieval Number: B7405129219/2020©BEIESP | DOI: 10.35940/ijitee.B7405.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.
Keywords: Multiplier, Dadda Algorithm, Gate Diffusion Input (GDI), Pass Transistor logic (PTL), CMOS Process Technology, Cadecne(tool)
Scope of the Article: Algorithm Engineering