Architecture of 2X2 FIR Filter using Vedic Multiplier and Brent-Kung Adder
Abhishek Bhatt1, Fatima2
1Dr. Abhishek Bhatt*, Professor, Department of ECE, Technocrats Institute of Technology, Bhopal (M.P), India.
2Ms. Fatima, M. Tech Scholar, Department of ECE, Technocrats Institute of Technology, Bhopal (M.P), India.
Manuscript received on February 10, 2020. | Revised Manuscript received on February 21, 2020. | Manuscript published on March 10, 2020. | PP: 1638-1642 | Volume-9 Issue-5, March 2020. | Retrieval Number: E3070039520/2020©BEIESP | DOI: 10.35940/ijitee.E3070.039520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposed, a 2X2 FIR filter which is based on the Brent-Kung adder and Vedic multiplier. A 2X2 FIR filter has been designed using Brent-Kung-Adder (BKA) and filter coefficient. Verilog platform and Xilinx 14.5 software. The Brent Kung adder is much faster than the look ahead carry adder (LACD), carry select adder and ripple carry adder (RCA) and it is a parallel prefix adder. Lowarea and the power consumption in Brent-kung adder is also less as compared to various adders. Multiplication of a number using the Vedic multiplier is arithmetic key operation to be performed with low power consumption of and increase the speed in the consequence applications. Proposed design utilize the common multiplication in cross multiply to compensate the problem of delay which is occurring in the Booth Multiplier and Array Multiplier and etc. Brent-kung adder used to decrease the delay which was occur in the multiplier and significantly reduce the quantity of logic elements such as gates, signals etc.
Keywords: Brent-kung Adder, FIR Filter, Delay, Parallel Prefix Adder, Vedic Multiplier.
Scope of the Article: Computer Architecture and VLSI